A 1.8/3.3V CMOS Low Power Output Pad

In this paper a dual voltage CMOS low power output pad is presented. The pads are the interface circuits between the core and the package pins of any integrated circuit. The power consumption of these pads it is a very important parameter for the global power consumption of the integrated circuit that includes them. The proposed pad includes a pre-driver and a final output stage including ESD(electro-static discharge) protection circuit. Both the final output stage and the pre-driver are designed under low power demands with high driving load current capabilities. A 0.18um CMOS technology is used to implement the layout of the output pad. The post-layout simulation results for 12mA output current show that the total parasitic power consumption is less than 160uW and a maximum value of 4nA for the leakage current consumption.